The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. High packing density, low heat generation, and low power consumption, with good reliability and long operation life must be maintained without any functional device degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size.
As integrated circuits become denser, the widths of interconnect layers that connect transistors and other semiconductor devices of the integrated circuit are reduced. As the widths of interconnect layers and semiconductor devices decrease, their resistance increases. As a result, semiconductor manufacturers seek to create smaller and faster devices by using, for example, a copper interconnect instead of a traditional aluminum interconnect. Unfortunately, copper is very difficult to etch in most semiconductor process flows. Therefore, damascene processes have been proposed and implemented to form copper interconnects.
Damascene methods usually involve forming a trench and/or an opening in a dielectric layer that lies beneath and on either side of the copper-containing structures. Once the trenches or openings are formed, a blanket layer of the copper-containing material is formed over the entire device. Electrochemical deposition (ECD) is typically the only practical method to form a blanket layer of copper. The thickness of such a layer must be at least as thick as the deepest trench or opening. After the trenches or openings are filled with the copper-containing material, the copper-containing material over them is removed, e.g., by chemical-mechanical planarization (CMP), so as to leave the copper containing material in the trenches and openings but not over the dielectric or over the uppermost portion of the trench or opening.
During CMP, copper and the adjacent dielectric are removed from the wafer at different rates. Typically, a copper-selective chemical slurry is applied, after which a first round of polishing occurs. Then, a dielectric-selective slurry is applied, followed by more polishing. This process creates certain surface anomalies, and a varying post-CMP topography. A number of factors, including pattern geometry (e.g., copper line density), affect the removal rates and add to the surface anomalies. One common surface anomaly that occurs with copper CMP is dishing. Dishing occurs when the copper recedes below or protrudes above the level of the adjacent dielectric. Theoretically, the goal of the CMP process is to achieve a flat post-CMP topography, as excessive dishing can negatively impact process yields. In practice, however, some processes may achieve optimal yields with a slight, or even moderate, amount of dishing. Regardless of whether a flat or slightly dished topology is desired, the ability to monitor and actively control the amount of dishing is critical to achieving optimal process yields.
A number of conventional methods exist by which post-CMP topography can be measured or profiled. Typically, such characterization is referred to as metrology. Unfortunately, a number of such conventional methods are destructive in nature, or are limited in scope to very small test areas on a wafer. As such, these approaches are not of much use for high-volume, in-process applications. More common in these applications is the use of profilometry—a typically non-destructive process that involves physical movement of a stylus along the surface of a wafer. Unfortunately, however, current profilometry approaches provide only the ability to render a relative physical measurement or characterization of post-CMP topography. They do not provide the ability to actively control the CMP process based on metrology data.
There are some existing methods that attempt to modify post-CMP topologies in response to profilometry data. Unfortunately, there are certain drawbacks associated with each. Most conventional methods either require additional processing steps or changes to device layout and design—adding costs to and reducing the efficiency of production processes. These approaches augment, instead of optimize, the already existing process steps. Additionally, many such conventional methods tend to be rather static in nature. Dynamic modification of CMP on a wafer-to-wafer, or even lot-to-lot, basis in order to address subtle variations in metrology data is simply not possible or not operationally feasible. The substantial effort and cost associated with modifying the CMP process often translates into substantial yield losses to dishing before a change can be justified. Furthermore, many such approaches are not designed for concurrent, cooperative use with comprehensive profilometry systems and methods.
As a result, there is a need for a versatile system for controlling the post-CMP topology of semiconductor wafer—a system that provides direct and dynamic control of CMP processing, and concurrent, cooperative use with comprehensive profilometry evaluation, in an easy, efficient and cost-effective manner.